1. Field of the Invention
This application relates to fractional-N phase-locked loops and more particularly to correcting shortcomings in such phase-locked loops (PLLs).
2. Description of the Related Art
Wide band fractional-N PLLs see increasing demand in various fields, especially wireless communications. Large bandwidth of the PLL helps suppress the intrinsic noise of the VCO, and provides fast settling time during frequency switching.
Unlike an integer-N PLL, the feedback divider output clock (fbclk) leads and lags the reference clock (refclk) regularly in a fractional-N PLL due to an ever-changing frequency divider ratio. The change is necessary to maintain an average VCO clock to reference clock frequency ratio that contains a fraction. This quantization noise of the feedback clock phase is injected through the phase-frequency detector (PFD) and charge pump (CP), and easily becomes the dominant noise source of the system. Meanwhile, the CP exhibits nonlinearity, mainly due to the size mismatch between the up and down current sources. High frequency quantization noise is modulated by the nonlinearity down into the pass band of the PLL, corrupting the output clock.
Referring to FIG. 1, illustrated is a typical tri-state PFD used to drive the charge pump of a PLL. In locked steady state operation, the rising edge of the refclk triggers the up output pulse and the rising edge of the fbclk triggers the down output pulse. A short delay after both pulses rise, the PFD is reset and both pulses clear simultaneously (FIG. 1(b)). The total charge Q delivered by the charge pump to the loop filter isQ=Iup·td−Idn·t−Idn·td when fbclk leads, andQ=Iup·(−t)+Iup·td−Idn·td when fbclk lags. Here t is the time by which the fbclk leads refclk, td is the delay of reset in the PFD, and Iup and Idn are the value of up and down current sources. Q is nonlinear with respect to t if Iup≠Idn, causing the high frequency quantization noise in the phase of fbclk to alias into the PLL bandwidth.
Another source of error as described above is the quantization noise due to the feedback divider output clock (fbclk) leading and lagging the reference clock (refclk) regularly in a fractional-N PLL due to an ever-changing frequency divider ratio. The common approach to quantization noise reduction is to add dedicated current sources to implement a canceling digital to analog converter (DAC), which delivers a charge that is nearly the opposite of the quantization noise. A typical fractional-NPLL with quantization noise reduction is shown in FIG. 1C. The delta-sigma modulator (DSM) 150 not only determines the instantaneous feedback divider ratio for multi-modulus divider 152, but also provides the phase difference of the fbclk relative to the refclk for the digital control circuit 154 for the cancellation digital to analog converter (DAC) 156. The DAC 156 is typically a separate bank of current sources, each of which may turn on for a short duration that is approximately aligned with the charge pump (CP) current pulses. The DAC is controlled by a second delta-sigma modulator (DAC DSM) 154 that modulates its own quantization noise out of the PLL pass band. The penalties to pay for the added circuit components include thermal and 1/f noise, switch charge injection, error charge due to component mismatch, device leakage current and supply current. While the average total current is zero, the different current pulses have different amplitude, duration and skew, resulting in residual noise at high frequencies.
Thus, improvements at controlling noise, charge injection, mismatch error and leakage current in a PLL are desirable.